PIC18F4431 |
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CONFIG1H (address:0x300001, mask:0xCF) |
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OSC -- Oscillator Selection bits |
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OSC = LP |
0xF0 |
LP oscillator. |
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OSC = XT |
0xF1 |
XT oscillator. |
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OSC = HS |
0xF2 |
HS oscillator. |
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OSC = RC2 |
0xF3 |
External RC oscillator, CLKO function on RA6. |
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OSC = EC |
0xF4 |
EC oscillator, CLKO function on RA6. |
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OSC = ECIO |
0xF5 |
EC oscillator, port function on RA6. |
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OSC = HSPLL |
0xF6 |
HS oscillator, PLL enabled (clock frequency = 4 x FOSC1). |
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OSC = RCIO |
0xF7 |
External RC oscillator, port function on RA6. |
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OSC = IRCIO |
0xF8 |
Internal oscillator block, port function on RA6 and port function on RA7. |
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OSC = IRC |
0xF9 |
Internal oscillator block, CLKO function on RA6 and port function on RA7. |
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OSC = RC1 |
0xFA |
101X External RC oscillator, CLKO function on RA6. |
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OSC = RC |
0xFC |
11XX External RC oscillator, CLKO function on RA6. |
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FCMEN -- Fail-Safe Clock Monitor Enable bit |
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FCMEN = OFF |
0xBF |
Fail-Safe Clock Monitor disabled. |
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FCMEN = ON |
0xFF |
Fail-Safe Clock Monitor enabled. |
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IESO -- Internal External Oscillator Switchover bit |
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IESO = OFF |
0x7F |
Internal External Switchover mode disabled. |
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IESO = ON |
0xFF |
Internal External Switchover mode enabled. |
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CONFIG2L (address:0x300002, mask:0x0F) |
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PWRTEN -- Power-up Timer Enable bit |
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PWRTEN = ON |
0xFE |
PWRT enabled. |
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PWRTEN = OFF |
0xFF |
PWRT disabled. |
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BOREN -- Brown-out Reset Enable bits |
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BOREN = OFF |
0xFD |
Brown-out Reset disabled. |
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BOREN = ON |
0xFF |
Brown-out Reset enabled. |
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BORV -- Brown Out Reset Voltage bits |
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BORV = 45 |
0xF3 |
VBOR set to 4.5V. |
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BORV = 42 |
0xF7 |
VBOR set to 4.2V. |
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BORV = 27 |
0xFB |
VBOR set to 2.7V. |
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BORV = 20 |
0xFF |
Reserved. |
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CONFIG2H (address:0x300003, mask:0x3F) |
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WDTEN -- Watchdog Timer Enable bit |
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WDTEN = OFF |
0xFE |
WDT disabled (control is placed on the SWDTEN bit). |
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WDTEN = ON |
0xFF |
WDT enabled. |
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WDPS -- Watchdog Timer Postscale Select bits |
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WDPS = 1 |
0xE1 |
1:1. |
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WDPS = 2 |
0xE3 |
1:2. |
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WDPS = 4 |
0xE5 |
1:4. |
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WDPS = 8 |
0xE7 |
1:8. |
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WDPS = 16 |
0xE9 |
1:16. |
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WDPS = 32 |
0xEB |
1:32. |
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WDPS = 64 |
0xED |
1:64. |
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WDPS = 128 |
0xEF |
1:128. |
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WDPS = 256 |
0xF1 |
1:256. |
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WDPS = 512 |
0xF3 |
1:512. |
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WDPS = 1024 |
0xF5 |
1:1024. |
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WDPS = 2048 |
0xF7 |
1:2048. |
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WDPS = 4096 |
0xF9 |
1:4096. |
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WDPS = 8192 |
0xFB |
1:8192. |
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WDPS = 16384 |
0xFD |
1:16384. |
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WDPS = 32768 |
0xFF |
1:32768. |
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WINEN -- Watchdog Timer Window Enable bit |
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WINEN = ON |
0xDF |
WDT window enabledbled. |
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WINEN = OFF |
0xFF |
WDT window disabled. |
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CONFIG3L (address:0x300004, mask:0x3C) |
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PWMPIN -- PWM output pins Reset state control |
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PWMPIN = ON |
0xFB |
PWM outputs drive active states upon Reset. |
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PWMPIN = OFF |
0xFF |
PWM outputs disabled upon Reset (default). |
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LPOL -- Low-Side Transistors Polarity |
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LPOL = LOW |
0xF7 |
PWM0, 2, 4 and 6 are active-low. |
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LPOL = HIGH |
0xFF |
PWM0, 2, 4 and 6 are active-high. |
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HPOL -- High-Side Transistors Polarity |
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HPOL = LOW |
0xEF |
PWM1, 3, 5 and 7 are active-low. |
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HPOL = HIGH |
0xFF |
PWM1, 3, 5 and 7 are active-high. |
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T1OSCMX -- Timer1 Oscillator MUX |
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T1OSCMX = OFF |
0xDF |
Standard (legacy) Timer1 oscillator operation. |
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T1OSCMX = ON |
0xFF |
Low-power Timer1 operation when microcontroller is in Sleep mode. |
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CONFIG3H (address:0x300005, mask:0x9D) |
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FLTAMX -- FLTA MUX bit |
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FLTAMX = RD4 |
0xFE |
FLTA input is multiplexed with RD4. |
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FLTAMX = RC1 |
0xFF |
FLTA input is multiplexed with RC1. |
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SSPMX -- SSP I/O MUX bit |
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SSPMX = RD1 |
0xFB |
SCK/SCL clocks and SDA/SDI data are multiplexed with RD3 and RD2, respectively. SDO output is multiplexed with RD1. |
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SSPMX = RC7 |
0xFF |
SCK/SCL clocks and SDA/SDI data are multiplexed with RC5 and RC4, respectively. SDO output is multiplexed with RC7. |
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PWM4MX -- PWM4 MUX bit |
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PWM4MX = RD5 |
0xF7 |
PWM4 output is multiplexed with RD5. |
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PWM4MX = RB5 |
0xFF |
PWM4 output is multiplexed with RB5. |
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EXCLKMX -- TMR0/T5CKI External clock MUX bit |
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EXCLKMX = RD0 |
0xEF |
TMR0/T5CKI external clock input is multiplexed with RD0. |
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EXCLKMX = RC3 |
0xFF |
TMR0/T5CKI external clock input is multiplexed with RC3. |
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MCLRE -- MCLR Pin Enable bit |
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MCLRE = OFF |
0x7F |
Disabled. |
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MCLRE = ON |
0xFF |
Enabled. |
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CONFIG4L (address:0x300006, mask:0x85) |
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STVREN -- Stack Full/Underflow Reset Enable bit |
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STVREN = OFF |
0xFE |
Stack full/underflow will not cause Reset. |
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STVREN = ON |
0xFF |
Stack full/underflow will cause Reset. |
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LVP -- Low-Voltage ICSP Enable bit |
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LVP = OFF |
0xFB |
Low-voltage ICSP disabled. |
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LVP = ON |
0xFF |
Low-voltage ICSP enabled. |
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DEBUG -- Background Debugger Enable bit |
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DEBUG = ON |
0x7F |
Background debugger enabled; RB6 and RB7 are dedicated to In-Circuit Debug. |
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DEBUG = OFF |
0xFF |
Background debugger disabled; RB6 and RB7 configured as general purpose I/O pins. |
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CONFIG5L (address:0x300008, mask:0x0F) |
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CP0 -- Code Protection bit |
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CP0 = ON |
0xFE |
Block 0 (000200-000FFFh) code-protected. |
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CP0 = OFF |
0xFF |
Block 0 (000200-000FFFh) not code-protected. |
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CP1 -- Code Protection bit |
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CP1 = ON |
0xFD |
Block 1 (001000-001FFF) code-protected. |
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CP1 = OFF |
0xFF |
Block 1 (001000-001FFF) not code-protected. |
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CP2 -- Code Protection bit |
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CP2 = ON |
0xFB |
Block 2 (002000-002FFFh) code-protected. |
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CP2 = OFF |
0xFF |
Block 2 (002000-002FFFh) not code-protected. |
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CP3 -- Code Protection bit |
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CP3 = ON |
0xF7 |
Block 3 (003000-003FFFh) code-protected. |
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CP3 = OFF |
0xFF |
Block 3 (003000-003FFFh) not code-protected. |
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CONFIG5H (address:0x300009, mask:0xC0) |
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CPB -- Boot Block Code Protection bit |
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CPB = ON |
0xBF |
Boot Block (000000-0001FFh) code-protected. |
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CPB = OFF |
0xFF |
Boot Block (000000-0001FFh) not code-protected. |
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CPD -- Data EEPROM Code Protection bit |
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CPD = ON |
0x7F |
Data EEPROM code-protected. |
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CPD = OFF |
0xFF |
Data EEPROM not code-protected. |
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CONFIG6L (address:0x30000A, mask:0x0F) |
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WRT0 -- Write Protection bit |
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WRT0 = ON |
0xFE |
Block 0 (000200-000FFFh) write-protected. |
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WRT0 = OFF |
0xFF |
Block 0 (000200-000FFFh) not write-protected. |
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WRT1 -- Write Protection bit |
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WRT1 = ON |
0xFD |
Block 1 (001000-001FFF) write-protected. |
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WRT1 = OFF |
0xFF |
Block 1 (001000-001FFF) not write-protected. |
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WRT2 -- Write Protection bit |
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WRT2 = ON |
0xFB |
Block 2 (002000-002FFFh) write-protected. |
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WRT2 = OFF |
0xFF |
Block 2 (002000-002FFFh) not write-protected. |
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WRT3 -- Write Protection bit |
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WRT3 = ON |
0xF7 |
Block 3 (003000-003FFFh) write-protected. |
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WRT3 = OFF |
0xFF |
Block 3 (003000-003FFFh) not write-protected. |
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CONFIG6H (address:0x30000B, mask:0xE0) |
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WRTC -- Configuration Register Write Protection bit |
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WRTC = ON |
0xDF |
Configuration registers (300000-3000FFh) write-protected. |
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WRTC = OFF |
0xFF |
Configuration registers (300000-3000FFh) not write-protected. |
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WRTB -- Boot Block Write Protection bit |
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WRTB = ON |
0xBF |
Boot Block (000000-0001FFh) write-protected. |
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WRTB = OFF |
0xFF |
Boot Block (000000-0001FFh) not write-protected. |
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WRTD -- Data EEPROM Write Protection bit |
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WRTD = ON |
0x7F |
Data EEPROM write-protected. |
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WRTD = OFF |
0xFF |
Data EEPROM not write-protected. |
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CONFIG7L (address:0x30000C, mask:0x0F) |
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EBTR0 -- Table Read Protection bit |
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EBTR0 = ON |
0xFE |
Block 0 (000200-000FFFh) protected from table reads executed in other blocks. |
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EBTR0 = OFF |
0xFF |
Block 0 (000200-000FFFh) not protected from table reads executed in other blocks. |
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EBTR1 -- Table Read Protection bit |
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EBTR1 = ON |
0xFD |
Block 1 (001000-001FFF) protected from table reads executed in other blocks. |
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EBTR1 = OFF |
0xFF |
Block 1 (001000-001FFF) not protected from table reads executed in other blocks. |
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EBTR2 -- Table Read Protection bit |
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EBTR2 = ON |
0xFB |
Block 2 (002000-002FFFh) protected from table reads executed in other blocks. |
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EBTR2 = OFF |
0xFF |
Block 2 (002000-002FFFh) not protected from table reads executed in other blocks. |
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EBTR3 -- Table Read Protection bit |
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EBTR3 = ON |
0xF7 |
Block 3 (003000-003FFFh) protected from table reads executed in other blocks. |
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EBTR3 = OFF |
0xFF |
Block 3 (003000-003FFFh) not protected from table reads executed in other blocks. |
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CONFIG7H (address:0x30000D, mask:0x40) |
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EBTRB -- Boot Block Table Read Protection bit |
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EBTRB = ON |
0xBF |
Boot Block (000000-0001FFh) not protected from table reads executed in other blocks. |
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EBTRB = OFF |
0xFF |
Boot Block (000000-0001FFh) not protected from table reads executed in other blocks. |
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