nmx2 standard cell family

Inverting 2-way multiplexers
nmx2 symbol
The nmx2_x1 is a single stage inverting mux with a P/N ratio of 1.7. The control signal cmd can be 1 or 2 delay stages with a stage effort of about 2. The nmx2_x4 is a 3 stage inverting mux with stage efforts of about 1.7 and 3.9. The control signal cmd can have 3 or 4 stages with stage efforts of about 1, 1.7 and 3.9.
nq:((i0*cmd')+(i1*cmd))' cell width power Generic 0.13um typical timing (ps & ps/fF), pin i0.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
sxlib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
nmx2_x1 2.3  70 3.85 1.73  24.4  7.2f  73  2.91  53  1.85
nmx2_x4 4.0 120 6.60 2.77  65.2  4.4f 211  0.74 187  0.57
nmx2_x1
 
Effort
FO4 Log.
cmd /\ 2.04 2.90
¯_ 2.56
i0 /\ 1.87 1.98
¯_
i1 /\ 1.87 1.92
¯_
nmx2_x1 schematic nmx2_x1 standard cell layout
nmx2_x4
 
Effort
FO4 Log.
cmd /\ 2.90 0.67
¯_ 3.48
i0 /\ 3.01 0.34
¯_
i1 /\ 3.02 0.34
¯_
nmx2_x4 schematic nmx2_x4 standard cell layout