an2 standard cell family

2-I/P AND gate
an2 symbol
2 I/P AND gate designed with a large input stage. This reduces the delay, especially when the wire capacitance on the input pin is high. The stage effort is 1.2 for the an2_x05, 1.5 for the an2_x1 and 1.9 for the an2_x2.
z:(a*b) cell width power Generic 0.13um typical timing (ps & ps/fF), pin b.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
vxlib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
an2_x05 1.7  50 2.75  0.60  12.9  3.0f  70  4.94  87  3.81
an2_x1 1.7  50 2.75  0.88  18.2  3.9f  68  2.96  87  2.29
an2_x2 1.7  50 2.75 1.48  29.8  5.7f  69  1.56  87  1.20
an2_x05
 
Effort
FO4 Log.
a /\
¯_ 1.97
b /\
¯_ 1.87
an2_x05 schematic an2_x05 standard cell layout
an2_x1
 
Effort
FO4 Log.
a /\
¯_ 1.77
b /\
¯_ 1.69
an2_x1 schematic an2_x1 standard cell layout
an2_x2
 
Effort
FO4 Log.
a /\
¯_ 1.63
b /\
¯_ 1.56
an2_x2 schematic an2_x2 standard cell layout