nd2ab standard cell family |
2-I/P OR gate |
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The nd2ab gates are 2-OR gates made up as 2 inverters driving a NAND gate. According to the theory of logical effort, this combination should be faster than a regular or2 gate, and it is. The speed can be compared to the or2 gates, especially the or2v0x1 which has the same output P-transistor size as the nd2abv0x1. The nd2ab gates are bigger and consume more power than the or2 gates. | ||||||||||
z:(a+b) | cell width | power | Generic 0.13um typical timing (ps & ps/fF), pin b. | ||||||||
leakage | dynamic | tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF) | |||||||||
vsclib013 | gates | lambda | 0.13um | nW | nW/MHz | PinCap | PropR | RampR | PropF | RampF | |
nd2abv0x05 | 2.3 | 56 | 3.08 | 0.60 | 13.1 | 2.8f | 73 | 4.96 | 80 | 3.70 | |
nd2abv0x1 | 2.3 | 56 | 3.08 | 1.12 | 17.4 | 3.3f | 70 | 3.30 | 80 | 2.47 | |
nd2abv0x2 | 2.3 | 56 | 3.08 | 1.41 | 21.5 | 3.6f | 71 | 2.48 | 79 | 1.85 | |
nd2abv0x3 | 3.0 | 72 | 3.96 | 2.33 | 36.7 | 5.0f | 76 | 1.35 | 85 | 1.03 | |
nd2abv0x4 | 4.0 | 96 | 5.28 | 2.89 | 47.6 | 5.4f | 80 | 1.07 | 88 | 0.78 | |
Web data book for the vsclib. Vdd=1.2V, T=27°C, nominal process, generic 0.13um technology. Copyright © 2005-2007 Graham Petley. 05 JUL 2007 |