an4 standard cell family
4-I/P AND gate
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4 I/P AND gate designed with a large input stage. This reduces the delay, especially when the wire capacitance on the input pin is high.
z:(a*b*c*d)
cell width
power
Generic 0.13um typical timing (ps & ps/fF), pin
d
.
leakage
dynamic
tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
vxlib013
gates
lambda
0.13um
nW
nW/MHz
PinCap
PropR
RampR
PropF
RampF
an4_x1
2.3
70
3.85
1.30
23.6
4.3f
98
2.98
107
2.29
an4_x2
2.3
70
3.85
1.81
36.2
6.1f
97
1.57
105
1.21
an4_x3
3.0
90
4.95
2.58
44.2
6.9f
98
1.14
105
0.88
an4_x1
Effort
FO4
Log.
a
/\
¯_
2.55
b
/\
¯_
2.46
c
/\
¯_
2.29
d
/\
¯_
2.11
an4_x2
Effort
FO4
Log.
a
/\
¯_
2.31
b
/\
¯_
2.21
c
/\
¯_
2.08
d
/\
¯_
1.92
an4_x3
Effort
FO4
Log.
a
/\
¯_
2.23
b
/\
¯_
2.14
c
/\
¯_
2.01
d
/\
¯_
1.85
Web data book for the vxlib. V
dd
=1.2V, T=27°C, nominal process, generic 0.13um technology. Copyright © 2005-2007 Graham Petley. 28 MAY 2007