oai21 standard cell family

2-OR into 2-NAND gate
oai21 symbol
3 cells with different drive strengths, each with a P/N ratio of about 2. The width of the P-transistor connected to pin b is designed to have a similar conductivity to the two series P-transistors, so that there is a consistent output drive capability.
z:((a1+a2)*b)' cell width power Generic 0.13um typical timing (ps & ps/fF), pin a2.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
vxlib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
oai21_x05 1.7  50 2.75  0.52  10.2  3.8f  62  5.05  47  3.70
oai21_x1 1.7  50 2.75  0.87  16.1  5.9f  60  2.98  45  2.17
oai21_x2 2.3  70 3.85 1.69  29.0 10.8f  57  1.53  44  1.14
oai21_x05
 
Effort
FO4 Log.
a1 /\ 1.89 1.98
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a2 /\ 1.73 1.93
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b /\ 1.34 1.37
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oai21_x05 schematic oai21_x05 standard cell layout
oai21_x1
 
Effort
FO4 Log.
a1 /\ 1.80 1.86
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a2 /\ 1.62 1.77
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b /\ 1.25 1.22
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oai21_x1 schematic oai21_x1 standard cell layout
oai21_x2
 
Effort
FO4 Log.
a1 /\ 1.76 1.83
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a2 /\ 1.55 1.68
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b /\ 1.20 1.14
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oai21_x2 schematic oai21_x2 standard cell layout