xr2 standard cell family

2-I/P exclusive OR gate
xr2 symbol
2 XOR gates designed with an AND-OR Invert gate and 2 input inverters. The xr2_x4 then has a large output inverter to drive the output. The xr2_x1 is a 1/2 stage 2-XOR, and the xr2_x4 is a 2/3 stage 2-XOR. Stage efforts are about 2 for the inverter driving the AND-OR-Invert, and 3.5 driving the output inverter.
q:(i1^i0) cell width power Generic 0.13um typical timing (ps & ps/fF), pin i1.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
sxlib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
xr2_x1 3.0  90 4.95 2.08  35.8 10.8f  88  2.90  78  1.85
xr2_x4 4.0 120 6.60 3.46  82.5 10.3f 142  0.74 168  0.59
xr2_x1
 
Effort
FO4 Log.
i0 /\ 2.44 3.08
¯_ 2.68
i1 /\ 2.42 3.14
¯_ 2.86
xr2_x1 schematic xr2_x1 standard cell layout
xr2_x4
 
Effort
FO4 Log.
i0 /\ 2.68 0.78
¯_ 2.43
i1 /\ 3.08 0.70
¯_ 2.12
xr2_x4 schematic xr2_x4 standard cell layout