nd2 standard cell family
2-I/P NAND gate
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Single stage 2-I/P NAND gates. 4 drive strengths with a P/N ratio of 2.
z:(a*b)'
cell width
power
Generic 0.13um typical timing (ps & ps/fF), pin
b
.
leakage
dynamic
tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
vxlib013
gates
lambda
0.13um
nW
nW/MHz
PinCap
PropR
RampR
PropF
RampF
nd2_x05
1.3
40
2.20
0.39
5.0
2.6f
46
4.94
36
3.68
nd2_x1
1.3
40
2.20
0.66
8.0
4.1f
45
2.96
35
2.16
nd2_x2
1.3
40
2.20
1.28
14.6
7.5f
44
1.52
34
1.11
nd2_x4
2.0
60
3.30
2.50
26.6
14.1f
43
0.78
34
0.56
nd2_x05
Effort
FO4
Log.
a
/\
1.27
1.31
¯_
b
/\
1.21
1.28
¯_
nd2_x1
Effort
FO4
Log.
a
/\
1.21
1.23
¯_
b
/\
1.17
1.21
¯_
nd2_x2
Effort
FO4
Log.
a
/\
1.17
1.17
¯_
b
/\
1.12
1.14
¯_
nd2_x4
Effort
FO4
Log.
a
/\
1.16
1.18
¯_
b
/\
1.09
1.10
¯_
Web data book for the vxlib. V
dd
=1.2V, T=27°C, nominal process, generic 0.13um technology. Copyright © 2005-2007 Graham Petley. 28 MAY 2007