nr3a standard cell family

3-I/P NOR gate with inverted input
nr3a symbol
Minimum size 3-I/P NOR gate with an inverted input. The output P/N ratio is about 1.7, and the gain from input a is about 1.6.
z:(a'+b+c)' cell width power Generic 0.13um typical timing (ps & ps/fF), pin c.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
vsclib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
nr3av0x05 2.3  56 3.08  0.81   7.7  3.7f  53  6.24  50  3.87
nr3av0x05
 
Effort
FO4 Log.
a /\
¯_ 2.52
b /\ 2.06 2.23
¯_
c /\ 1.81 2.19
¯_
nr3av0x05 schematic nr3av0x05 standard cell layout