xr2 standard cell family

2-I/P exclusive OR gate
xr2 symbol
2 XOR gates designed with an AND-OR Invert gate and 2 input inverters. The xr2_x4 then has a large output inverter to drive the output. The xr2_x1 is a 1/2 stage 2-XOR, and the xr2_x4 is a 2/3 stage 2-XOR. Stage efforts are about 2 for the inverter driving the AND-OR-Invert, and 3.5 driving the output inverter.
q:(i1^i0) cell width power Generic 0.13um typical timing (ps & ps/fF), pin i1.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
ssxlib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
xr2_x1 3.0  90 4.95 2.08  33.2  9.8f  87  3.03  76  2.00
xr2_x4 4.0 120 6.60 3.46  77.5  9.4f 142  0.76 164  0.62
xr2_x1
 
Effort
FO4 Log.
i0 /\ 2.42 3.07
¯_ 2.62
i1 /\ 2.36 3.04
¯_ 2.77
xr2_x1 schematic xr2_x1 standard cell layout
xr2_x4
 
Effort
FO4 Log.
i0 /\ 2.63 0.75
¯_ 2.42
i1 /\ 3.01 0.67
¯_ 2.11
xr2_x4 schematic xr2_x4 standard cell layout