oa2a22 standard cell family
2×2-AND into 2-OR gate
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2-2 I/P AND-OR gate with a stage effort of about 3.5 for the oa2a22_x2, and about 7 for the oa2a22_x4.
q:((i2*i3)+(i0*i1))
cell width
power
Generic 0.13um typical timing (ps & ps/fF), pin
i1
.
leakage
dynamic
tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
ssxlib013
gates
lambda
0.13um
nW
nW/MHz
PinCap
PropR
RampR
PropF
RampF
oa2a22_x2
3.0
90
4.95
1.39
30.0
4.0f
109
1.53
138
1.23
oa2a22_x4
3.3
100
5.50
2.08
46.6
3.9f
138
0.77
179
0.63
oa2a22_x2
Effort
FO4
Log.
i0
/\
¯_
2.12
i1
/\
¯_
2.08
i2
/\
¯_
2.49
i3
/\
¯_
2.55
oa2a22_x4
Effort
FO4
Log.
i0
/\
¯_
2.47
i1
/\
¯_
2.42
i2
/\
¯_
2.83
i3
/\
¯_
2.90
Web data book for the ssxlib. V
dd
=1.2V, T=27°C, nominal process, generic 0.13um technology. Copyright © 2005-2007 Graham Petley. 16 JUL 2007