nd2a standard cell family
2-I/P NAND gate with inverted input
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Single stage 2-I/P NAND gates with one inverted input. The output P:N ratio is about 2.3 and the stage effort on pin
a
is 1.2.
z:(a+b')
cell width
power
Generic 0.13um typical timing (ps & ps/fF), pin
a
.
leakage
dynamic
tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
rgalib013
gates
lambda
0.13um
nW
nW/MHz
PinCap
PropR
RampR
PropF
RampF
nd2av0x2
2.7
64
3.52
1.43
32.2
6.0f
63
2.12
82
1.84
nd2av0x2
Effort
FO4
Log.
a
/\
¯_
1.71
b
/\
1.18
1.21
¯_
Web data book for the rgalib. V
dd
=1.2V, T=27°C, nominal process, generic 0.13um technology. Copyright © 2005-2007 Graham Petley. 08 JUL 2007