nr4 standard cell family
4-I/P NOR gate
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The P/N ratio has been kept as close to 2 as possible for balanced output skew, even if this is not the fastest configuration.
z:(a+b+c+d)'
cell width
power
Generic 0.13um typical timing (ps & ps/fF), pin
d
.
leakage
dynamic
tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
vxlib013
gates
lambda
0.13um
nW
nW/MHz
PinCap
PropR
RampR
PropF
RampF
nr4_x05
2.0
60
3.30
0.73
10.2
4.6f
52
5.98
58
3.84
nr4_x1
3.0
90
4.95
1.41
51.8
10.5f
113
3.00
102
2.18
nr4_x05
Effort
FO4
Log.
a
/\
2.93
2.86
¯_
b
/\
2.77
2.76
¯_
c
/\
2.51
2.73
¯_
d
/\
2.09
2.64
¯_
nr4_x1
Effort
FO4
Log.
a
/\
2.03
2.64
¯_
b
/\
2.77
2.81
¯_
c
/\
2.47
2.73
¯_
d
/\
3.07
3.13
¯_
Web data book for the vxlib. V
dd
=1.2V, T=27°C, nominal process, generic 0.13um technology. Copyright © 2005-2007 Graham Petley. 28 MAY 2007