nd4 standard cell family

4-I/P NAND gate
nd4 symbol
The P/N ratio is set to 2.5, which is close to the P/N ratio of 2.6 which gives the fastest speed, as well as balanced rise and fall drive strengths.
z:(a*b*c*d)' cell width power Generic 0.13um typical timing (ps & ps/fF), pin d.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
vxlib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
nd4_x05 2.0  60 3.30  0.84   9.8  3.7f  58  4.25  44  3.83
nd4_x1 2.0  60 3.30 1.62  17.0  6.3f  55  2.20  42  2.02
nd4_x2 3.0  90 4.95 2.33  23.4  8.9f  53  1.52  40  1.41
nd4_x3 3.7 110 6.05 3.12  31.8 12.0f  54  1.13  41  1.05
nd4_x05
 
Effort
FO4 Log.
a /\ 1.89 1.77
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b /\ 1.81 1.76
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c /\ 1.73 1.79
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d /\ 1.58 1.74
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nd4_x05 schematic nd4_x05 standard cell layout
nd4_x1
 
Effort
FO4 Log.
a /\ 1.75 1.60
¯_
b /\ 1.68 1.59
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c /\ 1.59 1.59
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d /\ 1.45 1.55
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nd4_x1 schematic nd4_x1 standard cell layout
nd4_x2
 
Effort
FO4 Log.
a /\ 1.82 1.72
¯_
b /\ 1.71 1.67
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c /\ 1.59 1.62
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d /\ 1.41 1.51
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nd4_x2 schematic nd4_x2 standard cell layout
nd4_x3
 
Effort
FO4 Log.
a /\ 1.82 1.72
¯_
b /\ 1.74 1.71
¯_
c /\ 1.57 1.58
¯_
d /\ 1.42 1.52
¯_
nd4_x3 schematic nd4_x3 standard cell layout