xaon21 standard cell family

2-I/P exclusive OR gate with 2-AND input
xaon21 symbol
2 XOR gates with AND gate input designed for minimum transistor count and hence smallest size. The Prop and Ramp delays below are the average of the inverting and non-inverting delays. The Synopsys Liberty format .LIB file has the correct delays for each case.
z:((a1*a2)^b) cell width power Generic 0.13um typical timing (ps & ps/fF), pin a2.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
vxlib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
xaon21_x05 2.7  80 4.40  0.70  22.0  4.1f  96  4.78  92  3.87
xaon21_x1 2.7  80 4.40 1.35  37.8  7.2f  87  2.50  85  2.06
xaon21_x05
 
Effort
FO4 Log.
a1 /\ 1.90 1.58
¯_ 2.70
a2 /\ 1.95 1.69
¯_ 2.76
b /\ 2.19 2.75
¯_ 2.00
xaon21_x05 schematic xaon21_x05 standard cell layout
xaon21_x1
 
Effort
FO4 Log.
a1 /\ 1.78 1.49
¯_ 2.57
a2 /\ 1.75 1.49
¯_ 2.57
b /\ 2.05 2.59
¯_ 1.91
xaon21_x1 schematic xaon21_x1 standard cell layout