xor2 standard cell family

2-I/P exclusive OR gate
xor2 symbol
2-input XOR gate with output P/N ratio of about 1.28. The Prop and Ramp delays below are the average of the inverting and non-inverting delays. The Synopsys Liberty format .LIB file has the correct delays for each case.
z:(a^b) cell width power Generic 0.13um typical timing (ps & ps/fF), pin a.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
vgalib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
xor2v0x1 4.0  96 5.28 1.22  30.9  5.5f  90  3.63  79  1.85
xor2v0x1
 
Effort
FO4 Log.
a /\ 1.66 1.35
¯_ 2.47
b /\ 2.67 3.46
¯_ 2.33
xor2v0x1 schematic xor2v0x1 standard cell layout