oai23a standard cell family
2-OR and 3-OR into 2-NAND with inverted and shared inputs
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Minimum sized cell with a P/N ratio of about 2 on the output. Implemented as a 2-NAND followed by an 2x 2-OR into 2-NAND gate (oai22).
z:((b1'*b2')+(a3'*b1*b2))
cell width
power
Generic 0.13um typical timing (ps & ps/fF), pin
b2
.
leakage
dynamic
tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
vsclib013
gates
lambda
0.13um
nW
nW/MHz
PinCap
PropR
RampR
PropF
RampF
oai23av0x05
3.0
72
3.96
0.96
10.8
5.4f
88
7.24
89
4.97
oai23av0x05
Effort
FO4
Log.
a3
/\
1.79
1.82
¯_
b1
/\
2.76
3.82
¯_
3.81
b2
/\
2.57
3.66
¯_
3.72
Web data book for the vsclib. V
dd
=1.2V, T=27°C, nominal process, generic 0.13um technology. Copyright © 2005-2007 Graham Petley. 05 JUL 2007