xor2 standard cell family

2-I/P exclusive OR gate
xor2 symbol
2 XOR gates designed for minimum transistor count and hence smallest size. The Prop and Ramp delays below are the average of the inverting and non-inverting delays. The Synopsys Liberty format .LIB file has the correct delays for each case.
z:(a^b) cell width power Generic 0.13um typical timing (ps & ps/fF), pin a.
leakage dynamic tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
vxlib013 gates lambda 0.13um nW nW/MHz PinCap PropR RampR PropF RampF
xor2_x05 2.3  70 3.85  0.67  18.0  4.0f  80  4.89  79  3.62
xor2_x1 2.3  70 3.85 1.27  31.3  6.7f  75  2.57  75  1.91
xor2_x05
 
Effort
FO4 Log.
a /\ 1.73 1.57
¯_ 2.48
b /\ 2.09 2.45
¯_ 2.14
xor2_x05 schematic xor2_x05 standard cell layout
xor2_x1
 
Effort
FO4 Log.
a /\ 1.59 1.39
¯_ 2.28
b /\ 1.95 2.29
¯_ 1.99
xor2_x1 schematic xor2_x1 standard cell layout