mxi2 standard cell family
Inverting 2-way multiplexers
UP
PREV
NEXT
This two-way inverting mux uses a CMOS transfer gate for the fastest speed.
z:((a0*s')+(a1*s))'
cell width
power
Generic 0.13um typical timing (ps & ps/fF), pin
a0
.
leakage
dynamic
tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
rgalib013
gates
lambda
0.13um
nW
nW/MHz
PinCap
PropR
RampR
PropF
RampF
mxi2v2x1
4.0
96
5.28
1.66
27.9
6.1f
75
2.54
55
1.57
mxi2v2x1
Effort
FO4
Log.
a0
/\
1.64
1.45
¯_
a1
/\
1.62
1.37
¯_
s
/\
1.99
2.76
¯_
1.87
Web data book for the rgalib. V
dd
=1.2V, T=27°C, nominal process, generic 0.13um technology. Copyright © 2005-2007 Graham Petley. 08 JUL 2007