nr3 standard cell family
3-I/P NOR gate
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The P/N ratio has been kept as close to 2 as possible for balanced output skew, even if this is not the fastest configuration.
z:(a+b+c)'
cell width
power
Generic 0.13um typical timing (ps & ps/fF), pin
c
.
leakage
dynamic
tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
vxlib013
gates
lambda
0.13um
nW
nW/MHz
PinCap
PropR
RampR
PropF
RampF
nr3_x05
1.7
50
2.75
0.73
9.9
5.0f
50
4.48
49
2.88
nr3_x1
2.3
70
3.85
1.42
17.1
9.2f
45
2.23
47
1.54
nr3_x05
Effort
FO4
Log.
a
/\
2.16
2.22
¯_
b
/\
2.02
2.16
¯_
c
/\
1.75
2.12
¯_
nr3_x1
Effort
FO4
Log.
a
/\
2.23
2.37
¯_
b
/\
2.00
2.17
¯_
c
/\
1.65
2.01
¯_
Web data book for the vxlib. V
dd
=1.2V, T=27°C, nominal process, generic 0.13um technology. Copyright © 2005-2007 Graham Petley. 28 MAY 2007