o4 standard cell family
4-I/P OR gate
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4 I/P OR gate with a stage effort of about 3.4 for the o4_x2 and about 5.6 for the o4_x4.
q:(i2+i0+i1+i3)
cell width
power
Generic 0.13um typical timing (ps & ps/fF), pin
i3
.
leakage
dynamic
tR=PropR+RampR×Load(fF), tF=PropF+RampF×Load(fF)
ssxlib013
gates
lambda
0.13um
nW
nW/MHz
PinCap
PropR
RampR
PropF
RampF
o4_x2
2.3
70
3.85
1.50
33.5
4.4f
89
1.52
189
1.31
o4_x4
2.7
80
4.40
2.31
66.7
5.8f
149
0.79
270
0.70
o4_x2
Effort
FO4
Log.
i0
/\
¯_
2.91
i1
/\
¯_
2.70
i2
/\
¯_
3.08
i3
/\
¯_
2.34
o4_x4
Effort
FO4
Log.
i0
/\
¯_
2.82
i1
/\
¯_
2.48
i2
/\
¯_
3.12
i3
/\
¯_
3.24
Web data book for the ssxlib. V
dd
=1.2V, T=27°C, nominal process, generic 0.13um technology. Copyright © 2005-2007 Graham Petley. 16 JUL 2007