PIC18F6490 |
|
CONFIG1H (address:0x300001, mask:0x07) |
|
OSC -- Oscillator |
|
OSC = LP |
0xF0 |
LP oscillator. |
|
|
OSC = XT |
0xF1 |
XT oscillator. |
|
|
OSC = HS |
0xF2 |
HS oscillator. |
|
|
OSC = RC |
0xF3 |
External RC oscillator, CLKO function on RA6. |
|
|
OSC = EC |
0xF4 |
EC oscillator, CLKO function on RA6. |
|
|
OSC = ECIO |
0xF5 |
EC oscillator, port function on RA6. |
|
|
OSC = HSPLL |
0xF6 |
HS oscillator, PLL enabled (clock frequency = 4 x FOSC1). |
|
|
OSC = RCIO |
0xF7 |
External RC oscillator, port function on RA6. |
|
|
OSC = INTIO67 |
0xF8 |
Internal oscillator block, port function on RA6 and RA7. |
|
|
OSC = INTIO7 |
0xF9 |
Internal oscillator block, CLKO function on RA6, port function on RA7. |
|
|
FCMEN -- Fail-Safe Clock Monitor Enable |
|
FCMEN = OFF |
0xBF |
Fail-Safe Clock Monitor disabled. |
|
|
FCMEN = ON |
0xFF |
Fail-Safe Clock Monitor enabled. |
|
|
IESO -- Internal External Switch Over Mode |
|
IESO = OFF |
0x7F |
Oscillator Switchover mode disabled. |
|
|
IESO = ON |
0xFF |
Oscillator Switchover mode enabled. |
|
|
CONFIG2L (address:0x300002, mask:0x1F) |
|
PWRT -- Power Up Timer |
|
PWRT = ON |
0xFE |
PWRT enabled. |
|
|
PWRT = OFF |
0xFF |
PWRT disabled. |
|
|
BOREN -- Brown Out Detect |
|
BOREN = OFF |
0xF9 |
Brown-out Reset disabled in hardware and software. |
|
|
BOREN = ON |
0xFB |
Brown-out Reset enabled and controlled by software (SBOREN is enabled). |
|
|
BOREN = NOSLP |
0xFD |
Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled). |
|
|
BOREN = SBORDIS |
0xFF |
Brown-out Reset enabled in hardware only (SBOREN is disabled). |
|
|
BORV -- Brown Out Voltage |
|
BORV = 0 |
0xE7 |
VBOR set to 4.6V. |
|
|
BORV = 1 |
0xEF |
VBOR set to 4.3V. |
|
|
BORV = 2 |
0xF7 |
VBOR set to 2.8V. |
|
|
BORV = 3 |
0xFF |
VBOR set to 2.1V. |
|
|
CONFIG2H (address:0x300003, mask:0x1F) |
|
WDT -- Watchdog Timer |
|
WDT = OFF |
0xFE |
WDT disabled (control is placed on the SWDTEN bit). |
|
|
WDT = ON |
0xFF |
WDT enabled. |
|
|
WDTPS -- Watchdog Postscaler |
|
WDTPS = 1 |
0xE1 |
1:1. |
|
|
WDTPS = 2 |
0xE3 |
1:2. |
|
|
WDTPS = 4 |
0xE5 |
1:4. |
|
|
WDTPS = 8 |
0xE7 |
1:8. |
|
|
WDTPS = 16 |
0xE9 |
1:16. |
|
|
WDTPS = 32 |
0xEB |
1:32. |
|
|
WDTPS = 64 |
0xED |
1:64. |
|
|
WDTPS = 128 |
0xEF |
1:128. |
|
|
WDTPS = 256 |
0xF1 |
1:256. |
|
|
WDTPS = 512 |
0xF3 |
1:512. |
|
|
WDTPS = 1024 |
0xF5 |
1:1024. |
|
|
WDTPS = 2048 |
0xF7 |
1:2048. |
|
|
WDTPS = 4096 |
0xF9 |
1:4096. |
|
|
WDTPS = 8192 |
0xFB |
1:8192. |
|
|
WDTPS = 16384 |
0xFD |
1:16384. |
|
|
WDTPS = 32768 |
0xFF |
1:32768. |
|
|
CONFIG3H (address:0x300005, mask:0x81) |
|
CCP2MX -- CCP2 Mux |
|
CCP2MX = PORTBE |
0xFE |
CCP2 input/output is multiplexed with RE7. |
|
|
CCP2MX = PORTC |
0xFF |
CCP2 input/output is multiplexed with RC1. |
|
|
LPT1OSC -- Low Power Timer1 Osc enable |
|
LPT1OSC = OFF |
0xFB |
Timer1 configured for higher power operation. |
|
|
LPT1OSC = ON |
0xFF |
Timer1 configured for low-power operation. |
|
|
MCLRE -- Master Clear Enable |
|
MCLRE = OFF |
0x7F |
RG5 input pin enabled; MCLR disabled. |
|
|
MCLRE = ON |
0xFF |
MCLR pin enabled; RG5 input pin disabled. |
|
|
CONFIG4L (address:0x300006, mask:0x81) |
|
STVREN -- Stack Overflow Reset |
|
STVREN = OFF |
0xFE |
Stack full/underflow will not cause Reset. |
|
|
STVREN = ON |
0xFF |
Stack full/underflow will cause Reset. |
|
|
XINST -- Extended Instruction Set Enable bit |
|
XINST = OFF |
0xBF |
Instruction set extension and Indexed Addressing mode disabled (Legacy mode). |
|
|
XINST = ON |
0xFF |
Instruction set extension and Indexed Addressing mode enabled. |
|
|
DEBUG -- Background Debugger Enable bit |
|
DEBUG = ON |
0x7F |
Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug. |
|
|
DEBUG = OFF |
0xFF |
Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins. |
|
|
CONFIG5L (address:0x300008, mask:0x01) |
|
CP -- Code Protect 00000-03FFF |
|
CP = ON |
0xFE |
Program memory block (000000-003FFFh) code-protected. |
|
|
CP = OFF |
0xFF |
Program memory block (000000-003FFFh) not code-protected. |
|