PIC18F2455 |
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CONFIG1L (address:0x300000, mask:0x00) |
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PLLDIV -- PLL Prescaler Selection bits |
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PLLDIV = 1 |
0xF8 |
No prescale (4 MHz oscillator input drives PLL directly). |
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PLLDIV = 2 |
0xF9 |
Divide by 2 (8 MHz oscillator input). |
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PLLDIV = 3 |
0xFA |
Divide by 3 (12 MHz oscillator input). |
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PLLDIV = 4 |
0xFB |
Divide by 4 (16 MHz oscillator input). |
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PLLDIV = 5 |
0xFC |
Divide by 5 (20 MHz oscillator input). |
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PLLDIV = 6 |
0xFD |
Divide by 6 (24 MHz oscillator input). |
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PLLDIV = 10 |
0xFE |
Divide by 10 (40 MHz oscillator input). |
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PLLDIV = 12 |
0xFF |
Divide by 12 (48 MHz oscillator input). |
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CPUDIV -- System Clock Postscaler Selection bits |
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CPUDIV = OSC1_PLL2 |
0xE7 |
[Primary Oscillator Src: /1][96 MHz PLL Src: /2]. |
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CPUDIV = OSC2_PLL3 |
0xEF |
[Primary Oscillator Src: /2][96 MHz PLL Src: /3]. |
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CPUDIV = OSC3_PLL4 |
0xF7 |
[Primary Oscillator Src: /3][96 MHz PLL Src: /4]. |
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CPUDIV = OSC4_PLL6 |
0xFF |
[Primary Oscillator Src: /4][96 MHz PLL Src: /6]. |
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USBDIV -- USB Clock Selection bit (used in Full-Speed USB mode only; UCFG:FSEN = 1) |
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USBDIV = 1 |
0xDF |
USB clock source comes directly from the primary oscillator block with no postscale. |
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USBDIV = 2 |
0xFF |
USB clock source comes from the 96 MHz PLL divided by 2. |
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CONFIG1H (address:0x300001, mask:0x05) |
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FOSC -- Oscillator Selection bits |
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FOSC = XT_XT |
0xF0 |
XT oscillator (XT). |
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FOSC = XTPLL_XT |
0xF2 |
XT oscillator, PLL enabled (XTPLL). |
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FOSC = ECIO_EC |
0xF4 |
EC oscillator, port function on RA6 (ECIO). |
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FOSC = EC_EC |
0xF5 |
EC oscillator, CLKO function on RA6 (EC). |
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FOSC = ECPLLIO_EC |
0xF6 |
EC oscillator, PLL enabled, port function on RA6 (ECPIO). |
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FOSC = ECPLL_EC |
0xF7 |
EC oscillator, PLL enabled, CLKO function on RA6 (ECPLL). |
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FOSC = INTOSCIO_EC |
0xF8 |
Internal oscillator, port function on RA6, EC used by USB (INTIO). |
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FOSC = INTOSC_EC |
0xF9 |
Internal oscillator, CLKO function on RA6, EC used by USB (INTCKO). |
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FOSC = INTOSC_XT |
0xFA |
Internal oscillator, XT used by USB (INTXT). |
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FOSC = INTOSC_HS |
0xFB |
Internal oscillator, HS oscillator used by USB (INTHS). |
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FOSC = HS |
0xFC |
HS oscillator (HS). |
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FOSC = HSPLL_HS |
0xFE |
HS oscillator, PLL enabled (HSPLL). |
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FCMEN -- Fail-Safe Clock Monitor Enable bit |
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FCMEN = OFF |
0xBF |
Fail-Safe Clock Monitor disabled. |
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FCMEN = ON |
0xFF |
Fail-Safe Clock Monitor enabled. |
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IESO -- Internal/External Oscillator Switchover bit |
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IESO = OFF |
0x7F |
Oscillator Switchover mode disabled. |
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IESO = ON |
0xFF |
Oscillator Switchover mode enabled. |
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CONFIG2L (address:0x300002, mask:0x1F) |
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PWRT -- Power-up Timer Enable bit |
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PWRT = ON |
0xFE |
PWRT enabled. |
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PWRT = OFF |
0xFF |
PWRT disabled. |
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BOR -- Brown-out Reset Enable bits |
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BOR = OFF |
0xF9 |
Brown-out Reset disabled in hardware and software. |
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BOR = SOFT |
0xFB |
Brown-out Reset enabled and controlled by software (SBOREN is enabled). |
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BOR = ON_ACTIVE |
0xFD |
Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled). |
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BOR = ON |
0xFF |
Brown-out Reset enabled in hardware only (SBOREN is disabled). |
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BORV -- Brown-out Reset Voltage bits |
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BORV = 0 |
0xE7 |
Maximum setting. |
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BORV = 1 |
0xEF |
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BORV = 2 |
0xF7 |
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BORV = 3 |
0xFF |
Minimum setting. |
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VREGEN -- USB Voltage Regulator Enable bit |
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VREGEN = OFF |
0xDF |
USB voltage regulator disabled. |
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VREGEN = ON |
0xFF |
USB voltage regulator enabled. |
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CONFIG2H (address:0x300003, mask:0x1F) |
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WDT -- Watchdog Timer Enable bit |
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WDT = OFF |
0xFE |
WDT disabled (control is placed on the SWDTEN bit). |
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WDT = ON |
0xFF |
WDT enabled. |
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WDTPS -- Watchdog Timer Postscale Select bits |
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WDTPS = 1 |
0xE1 |
1:1. |
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WDTPS = 2 |
0xE3 |
1:2. |
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WDTPS = 4 |
0xE5 |
1:4. |
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WDTPS = 8 |
0xE7 |
1:8. |
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WDTPS = 16 |
0xE9 |
1:16. |
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WDTPS = 32 |
0xEB |
1:32. |
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WDTPS = 64 |
0xED |
1:64. |
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WDTPS = 128 |
0xEF |
1:128. |
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WDTPS = 256 |
0xF1 |
1:256. |
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WDTPS = 512 |
0xF3 |
1:512. |
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WDTPS = 1024 |
0xF5 |
1:1024. |
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WDTPS = 2048 |
0xF7 |
1:2048. |
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WDTPS = 4096 |
0xF9 |
1:4096. |
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WDTPS = 8192 |
0xFB |
1:8192. |
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WDTPS = 16384 |
0xFD |
1:16384. |
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WDTPS = 32768 |
0xFF |
1:32768. |
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CONFIG3H (address:0x300005, mask:0x83) |
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CCP2MX -- CCP2 MUX bit |
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CCP2MX = OFF |
0xFE |
CCP2 input/output is multiplexed with RB3. |
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CCP2MX = ON |
0xFF |
CCP2 input/output is multiplexed with RC1. |
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PBADEN -- PORTB A/D Enable bit |
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PBADEN = OFF |
0xFD |
PORTB<4:0> pins are configured as digital I/O on Reset. |
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PBADEN = ON |
0xFF |
PORTB<4:0> pins are configured as analog input channels on Reset. |
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LPT1OSC -- Low-Power Timer 1 Oscillator Enable bit |
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LPT1OSC = OFF |
0xFB |
Timer1 configured for higher power operation. |
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LPT1OSC = ON |
0xFF |
Timer1 configured for low-power operation. |
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MCLRE -- MCLR Pin Enable bit |
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MCLRE = OFF |
0x7F |
RE3 input pin enabled; MCLR pin disabled. |
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MCLRE = ON |
0xFF |
MCLR pin enabled; RE3 input pin disabled. |
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CONFIG4L (address:0x300006, mask:0x85) |
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STVREN -- Stack Full/Underflow Reset Enable bit |
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STVREN = OFF |
0xFE |
Stack full/underflow will not cause Reset. |
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STVREN = ON |
0xFF |
Stack full/underflow will cause Reset. |
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LVP -- Single-Supply ICSP Enable bit |
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LVP = OFF |
0xFB |
Single-Supply ICSP disabled. |
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LVP = ON |
0xFF |
Single-Supply ICSP enabled. |
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XINST -- Extended Instruction Set Enable bit |
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XINST = OFF |
0xBF |
Instruction set extension and Indexed Addressing mode disabled (Legacy mode). |
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XINST = ON |
0xFF |
Instruction set extension and Indexed Addressing mode enabled. |
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DEBUG -- Background Debugger Enable bit |
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DEBUG = ON |
0x7F |
Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit Debug. |
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DEBUG = OFF |
0xFF |
Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins. |
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CONFIG5L (address:0x300008, mask:0x0F) |
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CP0 -- Code Protection bit |
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CP0 = ON |
0xFE |
Block 0 (000800-001FFFh) is code-protected. |
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CP0 = OFF |
0xFF |
Block 0 (000800-001FFFh) is not code-protected. |
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CP1 -- Code Protection bit |
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CP1 = ON |
0xFD |
Block 1 (002000-003FFFh) is code-protected. |
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CP1 = OFF |
0xFF |
Block 1 (002000-003FFFh) is not code-protected. |
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CP2 -- Code Protection bit |
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CP2 = ON |
0xFB |
Block 2 (004000-005FFFh) is code-protected. |
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CP2 = OFF |
0xFF |
Block 2 (004000-005FFFh) is not code-protected. |
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CONFIG5H (address:0x300009, mask:0xC0) |
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CPB -- Boot Block Code Protection bit |
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CPB = ON |
0xBF |
Boot block (000000-0007FFh) is code-protected. |
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CPB = OFF |
0xFF |
Boot block (000000-0007FFh) is not code-protected. |
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CPD -- Data EEPROM Code Protection bit |
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CPD = ON |
0x7F |
Data EEPROM is code-protected. |
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CPD = OFF |
0xFF |
Data EEPROM is not code-protected. |
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CONFIG6L (address:0x30000A, mask:0x0F) |
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WRT0 -- Write Protection bit |
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WRT0 = ON |
0xFE |
Block 0 (000800-001FFFh) is write-protected. |
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WRT0 = OFF |
0xFF |
Block 0 (000800-001FFFh) is not write-protected. |
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WRT1 -- Write Protection bit |
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WRT1 = ON |
0xFD |
Block 1 (002000-003FFFh) is write-protected. |
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WRT1 = OFF |
0xFF |
Block 1 (002000-003FFFh) is not write-protected. |
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WRT2 -- Write Protection bit |
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WRT2 = ON |
0xFB |
Block 2 (004000-005FFFh) is write-protected. |
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WRT2 = OFF |
0xFF |
Block 2 (004000-005FFFh) is not write-protected. |
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CONFIG6H (address:0x30000B, mask:0xE0) |
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WRTC -- Configuration Register Write Protection bit |
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WRTC = ON |
0xDF |
Configuration registers (300000-3000FFh) are write-protected. |
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WRTC = OFF |
0xFF |
Configuration registers (300000-3000FFh) are not write-protected. |
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WRTB -- Boot Block Write Protection bit |
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WRTB = ON |
0xBF |
Boot block (000000-0007FFh) is write-protected. |
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WRTB = OFF |
0xFF |
Boot block (000000-0007FFh) is not write-protected. |
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WRTD -- Data EEPROM Write Protection bit |
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WRTD = ON |
0x7F |
Data EEPROM is write-protected. |
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WRTD = OFF |
0xFF |
Data EEPROM is not write-protected. |
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CONFIG7L (address:0x30000C, mask:0x0F) |
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EBTR0 -- Table Read Protection bit |
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EBTR0 = ON |
0xFE |
Block 0 (000800-001FFFh) is protected from table reads executed in other blocks. |
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EBTR0 = OFF |
0xFF |
Block 0 (000800-001FFFh) is not protected from table reads executed in other blocks. |
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EBTR1 -- Table Read Protection bit |
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EBTR1 = ON |
0xFD |
Block 1 (002000-003FFFh) is protected from table reads executed in other blocks. |
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EBTR1 = OFF |
0xFF |
Block 1 (002000-003FFFh) is not protected from table reads executed in other blocks. |
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EBTR2 -- Table Read Protection bit |
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EBTR2 = ON |
0xFB |
Block 2 (004000-005FFFh) is protected from table reads executed in other blocks. |
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EBTR2 = OFF |
0xFF |
Block 2 (004000-005FFFh) is not protected from table reads executed in other blocks. |
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CONFIG7H (address:0x30000D, mask:0x40) |
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EBTRB -- Boot Block Table Read Protection bit |
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EBTRB = ON |
0xBF |
Boot block (000000-0007FFh) is protected from table reads executed in other blocks. |
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EBTRB = OFF |
0xFF |
Boot block (000000-0007FFh) is not protected from table reads executed in other blocks. |
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