PIC12F635 |
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CONFIG (address:0x2007, mask:0xFFFF) |
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FOSC -- Oscillator Selection bits |
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FOSC = LP |
0x3FF8 |
LP oscillator: Low-power crystal on RA5/T1CKI/OSC1/CLKIN and RA4/T1G/OSC2/CLKOUT. |
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FOSC = XT |
0x3FF9 |
XT oscillator: Crystal/resonator on RA5/T1CKI/OSC1/CLKIN and RA4/T1G/OSC2/CLKOUT. |
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FOSC = HS |
0x3FFA |
HS oscillator: High-speed crystal/resonator on RA5/T1CKI/OSC1/CLKIN and RA4/T1G/OSC2/CLKOUT. |
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FOSC = EC |
0x3FFB |
EC: I/O function on RA4/T1G/OSC2/CLKOUT, CLKIN on RA5/T1CKI/OSC1/CLKIN. |
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FOSC = INTOSCIO |
0x3FFC |
INTOSCIO oscillator: I/O function on RA4/T1G/OSC2/CLKOUT pin, I/O function on RA5/T1CKI/OSC1/CLKIN. |
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FOSC = INTOSCCLK |
0x3FFD |
INTOSC oscillator: CLKOUT function on RA4/T1G/OSC2/CLKOUT pin, I/O function on RA5/T1CKI/OSC1/CLKIN. |
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FOSC = EXTRCIO |
0x3FFE |
RCIO oscillator: I/O function on RA4/T1G/OSC2/CLKOUT pin, RC on RA5/T1CKI/OSC1/CLKIN. |
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FOSC = EXTRCCLK |
0x3FFF |
RC oscillator: CLKOUT function on RA4/T1G/OSC2/CLKOUT pin, RC on RA5/T1CKI/OSC1/CLKIN. |
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WDTE -- Watchdog Timer Enable bit |
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WDTE = OFF |
0x3FF7 |
WDT disabled and can be enabled by SWDTEN bit of the WDTCON register. |
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WDTE = ON |
0x3FFF |
WDT enabled. |
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PWRTE -- Power-up Timer Enable bit |
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PWRTE = ON |
0x3FEF |
PWRT enabled. |
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PWRTE = OFF |
0x3FFF |
PWRT disabled. |
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MCLRE -- MCLR pin function select bit |
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MCLRE = OFF |
0x3FDF |
MCLR pin function is alternate function, MCLR function is internally disabled. |
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MCLRE = ON |
0x3FFF |
MCLR pin is MCLR function and weak internal pull-up is enabled. |
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CP -- Code Protection bit |
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CP = ON |
0x3FBF |
Program memory is external read and write-protected. |
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CP = OFF |
0x3FFF |
Program memory is not code protected. |
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CPD -- Data Code Protection bit |
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CPD = ON |
0x3F7F |
Data memory is external read protected. |
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CPD = OFF |
0x3FFF |
Data memory is not code protected. |
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BOREN -- Brown-out Reset Selection bits |
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BOREN = OFF |
0x3CFF |
BOD and SBODEN disabled. |
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BOREN = SBODEN |
0x3DFF |
SBODEN controls BOD function. |
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BOREN = NSLEEP |
0x3EFF |
BOD enabled while running and disabled in Sleep. SBODEN bit disabled. |
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BOREN = ON |
0x3FFF |
BOD enabled and SBOdEN bit disabled. |
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IESO -- Internal-External Switchover bit |
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IESO = OFF |
0x3BFF |
Internal External Switchover mode disabled. |
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IESO = ON |
0x3FFF |
Internal External Switchover mode enabled. |
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FCMEN -- Fail-Safe Clock Monitor Enable bit |
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FCMEN = OFF |
0x37FF |
Fail-Safe Clock Monitor disabled. |
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FCMEN = ON |
0x3FFF |
Fail-Safe Clock Monitor enabled. |
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WURE -- Wake-Up Reset Enable bit |
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WURE = ON |
0x2FFF |
Wake-up and Reset enabled. |
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WURE = OFF |
0x3FFF |
Standard wake-up and continue enabled. |
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